1. Field of the Invention
The present invention relates to the field of computer memories, and more particularly, to improved apparatus and methods for memory organization.
2. Art Background
In computer systems, it is quite common to represent and convey information to a user through images that are digitally generated. These images may take a variety of forms, such as for example, alphanumeric characters, graphs, or pictorial representations of three dimensional objects. In many applications, the digital images are conveyed to a user on a display device, such as a raster scan color cathode ray tube (CRT), printer or the like. Typically, the images to be displayed are stored or generated in a digital form, manipulated, and then displayed.
In raster scan display systems, a CRT is employed which has a plurality of display elements, known as pixels, that are arranged along raster scan lines, as is common in the art. Each pixel is assigned a single bit digital value to represent foreground/background (as in a monochrome display system) or a multiple bit digital value to represent color (as in a color display system). Memories used to store representations of each pixel, compromising an image, are known as "mapped" or "frame buffer" memories.
As is commonly practiced in the art, the frame buffer is a dual-ported memory. A first port is dedicated to display refresh and a second port is dedicated to image updates. The frame buffer memory is typically time-sliced between the two ports, and more recent prior architectures employ a dynamic random access memory (DRAM), for use in video systems termed a "video memory DRAM", as the frame buffer memory which includes a very large serial shift register built into the video memory DRAM. In display refresh, an incrementing address is supplied to the DRAM input and the DRAM output data is first buffered and then serialized using high-speed shift registers. In such prior art architecture using a monochrome (black and white) display system, the frame buffer output data is typically sent directly over a cable to the CRT. In prior art architecture using a color system, the frame buffer output data is typically transmitted through a color look-up table and then to three digital to analog converters to drive a standard red-green-blue color monitor. The second image update port to video memory is coupled to a central processing unit or similar logic that is capable of manipulating and changing the data stored in the frame buffer.
Traditionally, the second update port of the frame buffer has been configured as an X-Y random access memory wherein the frame buffer is organized to have an X-coordinant and a Y-coordinant (one operation sets an X address, a second operation sets a Y address and a third operation reads or writes data space composed of 8-bit, 16-bit, 32-bit or larger width data values). In such prior art systems the processing logic coupled to the frame buffer memory has been a low-level, but relatively fast, microcoded local central processing unit or other similar bus master and the low-level interface to the local host CPU that operates on the frame buffer has been through high-level commands over a relatively slow serial link or direct memory access channel. More recent computer graphics architectures, including that of low-cost microcomputers, have transferred the graphics computational overhead from the serial link onto the host processor (e.g the Intel 80286 or the Motorola MC68020) or onto very large scale integrated chips (e.g NEC 7220), however, such systems have been limited to text operations. In either case, the low-level interface between the update port on the frame buffer memory and the logic providing the high level commands has been that of traditional Von-Nuemann architecture, to wit: linear instruction streams utilizing memory addresses corresponding to well defined memory or data cells.
Computers have traditionally addressed their memories in 8-bit, 16-bit, 32-bit or larger 2**N increments. One memory cycle has the capacity to transfer a predetermined number of bits and, of course, transferring data using the maximum possible data width maximizes performance. Hence, an 8-bit machine is typically inferior to a 16-bit machine and so on. For simplicty in the following descriptions we often try to use the term "byte" whenever possible; the reader should be aware that the mechanisms described may scale wider data paths.
In monochrome systems, the most reasonable method to increase performance is to organize or "map" the frame buffer memory so that a byte (8-bit) quantity will modify 8 adjacent pixels. As mentioned, the entire CRT screen is "mapped" in memory in this fashion and is commonly termed in the art as bit-mapping or "bit-mapped" displays. Bit values of "1" and "0" selectively chose between foreground and background (or vice-versa) in the accessed bit-map. Many recent personal microcomputers use this technique, however, machines traditionally falling under the category of "terminals" use character generators and do not fall in the category of "bit-mapped" displays.
In a memory mapped color system, however, each dot on the cathode ray tube (CRT) has three colors associated with it and each color will have a range of possible intensities. The number of bits typically used to encode the color intensities varies from 4 to 8 to 24 and up. A frame buffer stores these values which serve as indexes for a color look-up RAM. For example, an 8-bit frame buffer color value may index into a 256.times.24 RAM and a 24-bit output of this RAM may be split to drive three 8-bit red, green, blue, Digital-to-Analog converters. In all, systems that map the CRT screen in memory and which use color, each dot on the CRT is represented by a multiple-bit entity in the frame buffer. Prior art systems have organized memory arrays such that a byte transfer will transfer a particular value representing a particular pixel color to a specific X, Y location in the frame buffer array.
Such color display systems are often required to simultaneously display text or other 1-bit per pixel information and complex graphic images that require color values or other multi-bit per pixel information. However, when one bit per pixel information is required, prior art color systems require, because of their limited addressing architecture, an entire multi-bit data value to be transferred in order to convey 1 bit of information to a pixel. The improved memory organization of the present invention allows a color display system to have all the performance advantages and speed of a monochrome display (i.e. 1 bit of information affecting one pixel), while also being able to support traditional color applications (i.e. 1 multi-bit value affecting one pixel). Thus, a color display system using the improved memory organization of the present invention may operate simultaneously in a monochrome mode and in a traditional color mode. The memory organization of the present invention may be viewed as having a third port to the frame buffer to complement the single update port normally coupled to a frame buffer memory. Ignoring the video refresh port into the frame buffer memory, the traditional Von Nuemann precept of of one set of addresses selecting one set of datum has been modified to cause two sets of addresses to access the same set of data.
The following is a more detailed introductory explication to aid the reader in understanding the concepts introduced in the foregoing description.
For purposes of the specification contained herein, the term "map" or organization, is not restricted to a relationship of one bit stored in memory to one pixel, and is intended to include any set of bits representing a pixel, or other discrete device. Thus, a map or organization as used herein, is intended to include a plurality of bits, or sets of bits stored in memory which conveys one type of information to a pixel or other discrete device. Thus, a memory storing two types of information for a single pixel display may contain two organizations. As mentioned, in a monochrome display, typically, a multi-bit value stored in memory represents background (e.g. black) or foreground (e.g.white) at a corresponding plurality of pixels on a display screen. Each bit of this value having, for example, a logic of 1, would determine a foreground (black) at a corresponding pixel on a CRT, a 16 bit word would determine background or foreground at 16 corresponding pixels. Thus, text operations that require only background or foreground (a logic of 1 or 0) may be sufficiently determined by such a representation.
When color is desired to be displayed on a CRT, more information than a logic of 1 or 0 is needed to represent a color, at a corresponding pixel. In an 8 bit per pixel color system, colors are assigned values from the integers 0 to 255 and are digitally represented and stored in the memory array. When representing color on the display screen, the memory organization storing the color values becomes more complicated because in order to digitally map, in memory, values representing background/foreground at a corresponding plurality of pixels (referred to herein as word values) and a byte representing color at a single coresponding pixel, (referred to herein as "pixel values") in a single memory array, each pixel of the display CRT requires at least eight bits of information to be mapped into a memory array (2.sup.8 =256) for every pixel value. The present invention permits the organization of this color information into the same memory array used to store the background or foreground information so that text or font displays requiring only background/foreground may also be used, when desired, in addition to displaying color.
In FIG. 1, for purposes of illustration, there is shown a conceptual representation of a portion of such a dually mapped or organized memory array containing two separate sets of information (i.e. pixel color information and background/foreground information) stored in 128 memory cells. The term "memory cell" herein, refers to a digital memory element capable of storing only a single bit. Also, the following description, with reference to FIG. 1, employs the terms X-axis and Z-axis to designate alignment of data bits, however, it will be appreciated by one skilled in the art that these terms are for illustrative purposes and are not intended to restrict the invention to a particular alignment of data within the memory cells of FIG. 1, thus, the X and Z-axes of FIG. 1 are not necessarily orthogonal. Word values are stored in the memory cells of FIG. 1, along the X-axis in a plurality of rows, so that, with reference to FIG. 1, row 1 has stored therein sixteen 0 bits while cell row 2 has stored therein sixteen 1 bits. The bits stored in row 1 could be used to determine background/foreground at 16 adjacent pixels on a CRT screen while the bits stored in row 2 could be used to determine background/foreground at the same 16 adjacent pixels. Thus, the bits stored in rows 1 through 8 comprise eight word values that individually determine the background or foreground at 16 adjacent pixels on a CRT screen. Stored along the Z-axis, of the same memory cells of FIG. 1, are 16 columns, 0-15, that determine a color at the same 16 corresponding pixels on the CRT screen. In memory cell 1 of row 1, the first bit, having a logic of 0, which could be read to determine foreground at a single corresponding pixel, would also contain the first bit of an eight bit pixel byte used to designate a particular color to be displayed at a corresponding pixel on a CRT screen. The bit stored in memory cell 17 of row 2, having a logic of 1, would contain the second bit of an eight bit pixel value. Accordingly, the first left-hand bit of rows 1 through 8 also represent an eight bit color or pixel value that would be used to designate a particular color at a corresponding pixel of a CRT screen. In this fashion both background or foreground values, termed herein "word values" (defining a first organization) and color values, termed herein "pixel values" (defining a second organization) may be dually mapped in the same memory cells.
Traditionally, prior art color systems have employed only a Z-axis aligned addressing technique thus, if such a prior system used the memory organization of FIG. 1, 16 separate read or 16 separate write operations would be required in order to transfer a 16 bit X-aligned value such as the word value stored in row 1, in order to display simple black or white fonts of text. With reference to FIG. 1, in such a prior art system, as each Z-aligned value was transferred, the bits of each word read from or written to the memory array would have to be selected and composited in an adjacent device until, after 16 read or 16 write operations, the 16-bit word value stored in an X-axis aligned row could finally be determined by means of a complicated merge. This prior art process would have serious drawbacks. To obtain a desired 16 bit X-aligned word value 128 bits of Z-aligned byte information would have to be transferred along a bus. Since only sixteen bits of the 128 bits of information transferred comprise the desired 16 bit word value, such a prior art system would be much slower than it might otherwise be. The present invention overcomes the difficulties contained in the prior art by establishing a dually mapped or organized memory array and by addressing that array, in one memory cycle operation, along one coordinate, termed herein a "pixel-mode" and, in another memory cycle operation, along another coordinate termed herein a "word-mode". In the example of FIG. 1, if the pixel value in column 1, representing color at a particular pixel, were desired, in one write or read operation, all eight bits of the Z-axis aligned pixel value could be accessed and transferred. Similarly, if the word value in X-axis aligned row 1 is needed, that word may be transferred in a single read or write operation. In displaying objects on a screen, different pixels may require only word-mode values or only pixel-mode values from memory. The present invention allows greater flexibility, greater speed, and superior efficiency in transferring information stored in a digital memory and thus displaying that information on a display screen or other output receiving device.
For purposes of illustration, with reference to FIG. 1, we have termed the pixel bytes of columns 0-15 as being stored within a plurality of Z-axis aligned memory cells, however, since each pixel byte represents a color organized within memory so that it is mapped to a particular pixel on a CRT screen, the pixel values, stored in memory, form a matrix extending depthwise along the Z-axis, as is common the art. The present invention permits the word or X-aligned values,to be organized as a matrix forming a plurality a planes, as shown in FIG. 2, each plane representing the surface of a CRT screen. The word values of each plane as in FIG. 1, are stored in rows along an X-axis, however the pixel bytes extend depthwise into the word planes, along a Z-axis as shown in FIG. 3. Thus, the present invention establishes a 3-dimensional matrix of memory and provides data transfers to efficiently occur within this matrix.